Well supported advanced node, 40G = 45GS
Technology characteristics
Shrink technology: YES
Core voltage: 0.9V
I/O voltage: 2.5V (1.8V underdrive, 3.3V overdrive) or true 1.8V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well for low well sheet resistance and better latch-up behavior.
Optional Deep N-Well
<110> P- substrate wafer. Substrate resistivity 8-12ohm-cm
Dual Gate Oxide (1 for core, 1 for IO)
Vt options: lvt, svt, hvt, native
Temperature range: -40C to 125C
# of metals: 3 to 10 Cu + alrdl
Interconnect dielectric: ELK
Top metal: 3.1KA, 9KA, 12.5KA, 34KA
CMP on STI, contact, metals, vias and passivation
MoM
Passivation: dual layers
Options that need special attention
OTP/MTP
SRAM Cell
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer
Design tools
PDK: Cadence CDBA and OA, TSMC iPDK
Simulation tools
Hspice, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys, Magma, TSMC iDRC
Verification tools LVS
Cadence, Mentor Graphics, Synopsys, Magma, TSMC iLVS
Parasitic extraction tools
Cadence, Mentor Graphics, Synopsys
P&R tools
Cadence, Synopsys
Foundry IP
12-track / 9-track core cell libraries, multi-vt, coarse grain
0.9V/1.8V staggered (fail-safe digital, 5V input tolerant digital and regular analog) I/O library
0.9V/2.5V staggered (fail-safe digital, 5V input tolerant digital and regular analog) I/O library
SRAM compilers
MPW block size
9 mm2
