The 0.18 HV technololgy is based on the 1.8V/5V MS technology and adds 5V, 6V, 7V, 8V, 12V, 16V, 20V, 24V, 29V, 36V, 45V, 55V, 65V and 70V devices, aiming for high-voltage power management and automotive applications.
Technology characteristics
Shrink technology: NO
Pore voltage1.8V
I/O voltage 5V
Shallow Trench Isolation (STI)
Wells: Retrograde four well on -100- P- substrate wafer.
Four LV wells, two HV wells and N+ Buried Layer (NBL)
Substrate resistivity 8~12 ohm.cm on -100- P- substrate
Standard Vt
Temperature range -40C to 150C
# of metals: 3 to 6
Interconnect material: AlCu
Interconnect dielectric: FSG
Top metal: 8KA, 15KA, 30KA or 40KA
CMP on STI, contact, via and inter-metal dielectric layers
OTP / MTP
MoM
MiM: 1fF/µm2 or 2fF/µm2, mutual exclusive
Passivation: single
Wafer size
8 inch
Deliverables
# of dies (no wafer!): 40 dies / wafer
Design tools
PDK: Cadence CDBA and OA
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics
Verification tools LVS
Cadence, Mentor Graphics
Parasitic extraction tools
Cadence, Synopsys
P&R tools
Cadence, Synopsys
Foundry IP
10-track core cell library, with 5V I/O devices, SVt
1.8V/5V linear universal standard I/O
5V/5V linear universal standard I/O
SRAM compilers by ARM, Dolphin Integration, Synopsys
MPW block size
Min. 25 mm2, flexible aspect ratio
