TSMC 16nm CMOS logic FinFet Compact 0.8V/1.8V.
Technology characteristics
Shrink technology: 2% shrink
Core voltage: 0.8V
I/O voltage: 1.8V
Shallow Trench Isolation (STI)
Triple well, Deep N-Well in option
Dual gate oxide
Vt options: hvt, svt, lvt, ulvt, low noise vt
5V HVMOS
TiN High Resistor
N+/P+ metal gate allows symmetrical design of NMOS and PMOS devices
Temperature range: -40C to 125C
# of metals: 6 to 13 Cu plus last metal level in Al pad
Interconnect dielectric: ELK
HD MiM capacitors
Passivation: dual layers
12 inch wafers
Wafer size
12 inch
Deliverables
100 dies, no wafer
Design tools
PDK: TSMC iPDK
Simulation tools
Hspice, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys
Verification tools LVS
Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools
Cadence, Mentor Graphics, Synopsys
P&R tools
Cadence, Synopsys
Foundry IP
9-track, 7.5-track body biased core cell libraries with gate lengths of 16, 20 and 24nm
0.8V/1.8V hybrid staggered I/O library
SRAM compilers by TSMC, ARM_Artican, ARM ltd, GUC, Synopsys
MPW block size
4mm²
