Provide a general-purpose product for applications with a 1.0V core design and with 1.8, 2.5 or 3.3V capable IO’s for digital consumer, Networking , HDD and FPGA
Technology characteristics
Shrink technology: NO
Core voltage: 1.0V
I/O voltage: 1.8, 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on P-substrate
Tripple Well, Deep N-well (optional)
Multiple Vt options (lvt, svt, hvt, native)
Dual gate oxide and tripple gate oxide process
Temperature range: -40C to 125C
# of metals: 3 to 9 (+ALRDL)
Interconnect material: Cu + AlCu pad
LK inter-metal dielectric for thin metal
Top metal: 5.6 KA, 8.5KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
MS/RF options
MIM capacitor for MS & RF process: 1.0, 1.5, 2.0 fF/µm2(mutually exclusive)
High-Q copper inductor
Top metal: UTM, 34KA
Varactors
Dual passivation
Options that need special attention
Fuse RAM
Wafer size
12 inch
Deliverables
# of dies (no wafer!): 100 dies / wafer (12")
Design tools
PDK: Cadence CDBA, Cadence OA, Mentor, iPDK
Simulation tools
Hspice, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics
Verification tools LVS
Cadence, Mentor Graphics
Parasitic extraction tools
Cadence, Mentor Graphics
P&R tools
Cadence, Synopsys
Foundry IP
7,9,14-track core cell library, multi-Vt
1.0V/2.5V &1.0V/3.3V hybrid staggered slim I/O library that contains both standard and analog slim I/O
1.0V/2.5V &1.0V/3.3V linear staggered slim I/O library that contains both standard and analog slim I/O
1.0v/2.5v, 3.3v tolerant, staggered universal standard I/O
1.0V/3.3V, 5V Tolerant, Staggered Universal Standard I/O
SRAM compilers from 3rd party
MPW block size
16 mm2, flexible aspect ratio
