For applications in consumer electronics, computers, mobile computing, automotive electronics, IoT, and smart wearables.
Technology characteristics
Shrink technology: NO
Core voltage: 1.2V
I/O voltage: 2.5 or 3.3V
Shallow Trench Isolation (STI)
Wells: Retrograde twin well cmos technology on <100> P-substrate. Substrate resistivity 8-12ohm-cm
Tripple Well, Deep N-well (optional)
Vt options: lvt, svt, hvt,uhvt, native
Temperature range: -40C to 125C
# of metals: 3 to 8 +ALRDL
Interconnect dielectric: FSG
Top metal: 8KA
CMP on STI, contact, via and inter-metal dielectric layers
MoM
Varactors
MS/RF options
MIM capacitor for MS & RF process: 1fF/µm2
High-Q copper inductor
Top metal: UTM, 33.5K
Single passivation, Dual passivation optional
Wafer size
8/12 inch
Deliverables
# of dies (no wafer!): 40-dies (8"), 100 dies (12") / wafer
Design tools
PDK: Cadence CDBA and OA, Mentor
Simulation tools
Hspice, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics
Verification tools LVS
Cadence, Mentor Graphics
Parasitic extraction tools
Cadence, Mentor Graphics
P&R tools
Cadence, Synopsys
Foundry IP
9-track core cell library, with 5V I/O devices, SVt
1.2/3.3V regular,linear universal standard I/O
1.2V/2.5V & 1.2/3.3V Universal Analog I/O compatible with Linear Universal Standard I/O
1.2V/2.5V & 1.2/3.3V , hybrid linear slim I/O library that contains both standard and analog slim I/O
5V tolerant, linear universal standard I/O
1.2V/3.3V, 5V tolerant, staggered universal standard I/O
SRAM compilers from 3rd party
MPW block size
25 mm2, flexible aspect ratio
