TSMC 0.18 µm technology with 6 metal layers. Highly suited for MS/RF applications for today’s IoT and smart wearable innovations.
Technology characteristics
Shrink technology: NO
Pore voltage1.8V
I/O voltage 3.3V
Shallow Trench Isolation (STI)
Triple well (retrograde NW, PW and optional DNW)
Substrate resistivity 8~12 ohm.cm on <100> P- substrate
Standard Vt, Medium Vt NMOS and medium Vt PMOS, native NMOS
HRI poly resistor
Temperature range -40C to 125C
# of metals: 3 to 6
Interconnect material: AlCu
Interconnect dielectric: FSG
Top metal: 8KA, 20KA or 40KA
RDL: 8KA, limited offer in FAB8
Inductors
MoM
MiM: 1fF/µm2 or 2fF/µm2, mutual exclusive
Passivation: single
Options that need special attention
OTP / MTP
Wafer size
8 inch
Deliverables
40 dies / wafer
Design tools
Cadence CDBA, Cadence OA, TSMC iPDK
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Magma, Cadence, Synopsys, Mentor Graphics
Verification tools LVS
Magma, Cadence, Synopsys, Mentor Graphics
Parasitic extraction tools
Cadence, Synopsys, Mentor Graphics
P&R tools
Cadence, Synopsys
Foundry IP
Standard cells: 7-track. Gate density >= 140KGates / mm2
I/O library 3.3V
SRAM: from third party
MPW block size
Min. 25 mm2, flexible aspect ratio
