40 nm Logic and Mixed-Mode Low Power Process
Technology characteristics
Shrink technology: NO
Core voltage 0.9V
I/O voltage 1.8V, 2.5V
MOAT
Twin and triple well
Substrate resistivity 10~15 ohm.cm on Epi- substrate
LP_RVT, LP_HVT, LP_LVT, LP_UHVT
Temperature range -40C to 125C
# of metals: 10
Interconnect material: Cu
Interconnect dielectric: FSG
Top metal: 8kA, 12kA, 32.5kA
RDL: 12.5kA, 34kA
MoM
MiM: 2fF/µm2
Passivation: single
Wafer size
12 inch
Deliverables
90 samples
Design tools
Cadence CDBA, Laker
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys
Verification tools LVS
Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools
Cadence, Synopsys, Mentor Graphics
P&R tools
Cadence, Synopsys
Foundry IP
Standard cells
I/O library: NA
MPW block size
4000µm x 4000µm
