65 nm Logic and Mixed-Mode Standard Performance Low-K Process
Technology characteristics
Shrink technology: NO
Core voltage1.0V, 1.1V
I/O voltage 1.8V, 2.5V, 2.5_OD3.3V, 3.3V
MOAT
Twin and triple well
Substrate resistivity 7~17 ohm.cm on Epi - substrate
SP_RVT, SP_HVT, SP_LVT
Temperature range -40C to 125C
# of metals: 10
Interconnect material: Cu
Interconnect dielectric: FSG
Top metal: 8kA, 32.5kA
RDL: 12kA, 25kA, 36kA
Inductors
MoM
MiM: 2fF/µm2
Passivation: single
Wafer size
12 inch
Deliverables
90 samples
Design tools
Cadence CDBA, Laker
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys
Verification tools LVS
Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools
Cadence, Synopsys, Mentor Graphics
P&R tools
Cadence, Synopsys
Foundry IP
Standard cells
I/O library: NA
Dummy filling
by Foundry
MPW block size
4000µm x 4000µm
