0.11 µm Logic and Mixed-Mode 1P8M Metal Metal Capacitor Al Advanced Enhancement Process.
Technology characteristics
Shrink technology: YES
Core voltage: 1.2V
I/O voltage: 1.8V/2.5V/3.3V/5V
Shallow Trench Isolation (STI)
Triple well
Substrate resistivity 15~25 ohm.cm on <100> P- substrate
Vt options: HS, SP, LL, HS_SP, HS_LL, SP_LL and HS_SP_LL
Temperature range: -40C~125C
# of metals: 8
Interconnect material: AlCu
Dielectric: USG
Top metal: 20KA or 40KA
Inductors
MoM
MiM: 1.0fF/µm2 or 1.5fF/µm2 or 2.0fF/µm2
Passivation: single
Wafer size
8 inch
Deliverables
# of dies (no wafer!): 50 on an MPW, 25 on a mini@sic
Design tools
Cadence CDBA, Laker
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys
Verification tools LVS
Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools
Cadence, Mentor Graphics, Synopsys
P&R tools
Cadence, Synopsys
Foundry IP
Gate density
I/O voltage, OD, UD
RAM/ROM/Dual port/register files)
MPW block size
5mm x 5mm
