0.13 µm Mixed-Mode and RFCMOS 1P8M Metal Metal Capacitor FSG Enhancement Process
Technology characteristics
Shrink technology: NO
Core voltage1.2V
I/O voltage 2.5V or 3.3V
Shallow Trench Isolation (STI)
Twin and triple well
Substrate resistivity 15~25 ohm.cm on <100> P- substrate
HS, LL, SP, HS_SP, HS_LL, SP_LL, HS Native Vt, SP Native Vt
Temperature range -40C to 125C
# of metals: 5 to 8
Interconnect material: Cu
Dielectric: FSG
Top metal: 8KA, 20KA
Inductors
MoM
MiM: 1fF/µm2 or 1.5fF/µm2, mutual exclusive
Passivation: single
Wafer size
12 inch
Deliverables
90 dies / wafer on MPW, 45 dies / wafer on mini@sic
Design tools
Cadence CDBA, Laker
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys
Verification tools LVS
Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools
Cadence, Mentor Graphics, Synopsys
P&R tools
Cadence, Synopsys
Foundry IP
Standard cells
I/O library: NA
MPW block size
5mm x 5mm
