UMC L180 MM/RF 1.8V/3.3V 1P6M technology
Technology characteristics
Shrink technology: NO
Core voltage: 1.8V
I/O voltage: 3.eV
Shallow Trench Isolation (STI)
Triple well
Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate
Std Vt, 3.3V LVt PMOS, 3.3V LVt NMOS, 1.8V LVt PMOS, 1.8V LVt NMOS, 3.3V zero_Vt NMOS
Temperature range: -40C to 125C
# of metals: 6
Interconnect material: Al
Dielectric: FSG
Top metal: 8KA, 12 KA or 20KA
Inductors
MoM
MiM: 1fF/µm2
Passivation: single
Options that need special attention
OTP
Wafer size
8 inch
Deliverables
# of dies: 50 for an MPW, 25 for a mini@sic run
Design tools
Cadence CDBA, Cadence OA, Laker, Mentor, Tanner, ADS
Simulation tools
eldo, hspice, spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys
Verification tools LVS
Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools
Cadence, Mentor Graphics, Synopsys
P&R tools
Cadence, Synopsys
Foundry IP
Faraday standard cell libraries
Faraday I/O library 3.3V
Faraday memories
MPW block size
5mm x 5mm
