UMC 0.18 µm 1.8V/3.3V 1P6M logic process with embedded Flash/EEPROM memories
Technology characteristics
Shrink technology: NO
Core voltage: 1.8V
I/O voltage: 3.3V
Shallow Trench Isolation (STI)
Triple well
Substrate resistivity: 15~25 Ohm.cm on <100> P- substrate
Std Vt, 3.3V LVt PMOS, 3.3V LVt NMOS, 1.8V LVt PMOS, 1.8V LVt NMOS, 3.3V zero_Vt NMOS, 14V HV, 6.5V MV
Temperature range: -40C to 125C
# of metals: 6
Interconnect material: Al
Dielectric: FSG
Top metal: 8KA, 12 KA
Inductors
MoM
MiM: 1fF/µm2
Passivation: single
Wafer size
8 inch
Deliverables
# of dies: 50 for an MPW, 25 for a mini@sic run
Design tools
Cadence CDBA, Laker
Simulation tools
HSPICE, Eldo, Spectre
Verification tools DRC
Cadence, Mentor Graphics, Synopsys
Verification tools LVS
Cadence, Mentor Graphics, Synopsys
Parasitic extraction tools
Cadence, Mentor Graphics, Synopsys
P&R tools
Cadence, Synopsys
Foundry IP
Faraday standard cell libraries
Faraday I/O library 3.3V
Faraday memories
MPW block size
5mm x 5mm
