DB HiTek supports analog IC design with a modular process at the 0.18um node. This process gives customers the flexibility to choose an option that best meets their needs. Our HP180 option, for example, is ideal for implementing high-voltage devices used in high-precision medical or industrial equipment.
0.18um General Logic
- Foundry Compatible DR & Process
- Mass Production over 2M wfs since 2003
- DBH own IPs/Libs
- Available 90% and 85% optical shrink process
0.18um Analog Specialized
- Low Noise with Pure Ox + Buried Channel
- Well Analog Characterized Res. and Cap.
- Good Mismatching
- Available High Voltage (7V ~ 30V)
- HP18 Process Overview
. 0.18um High Precision Analog CMOS
. 1.8V CMOS / 5V CMOS / ~24V DEMOS
. Low Noise Components : Buried Channel PMOS, JFET, BJT
. High Precision Characteristics : Good Si to Model matching, Low mismatching factor, Well characterized Res. & Cap,
Low DA Cap.
. NVM : ~128bit Poly fuse, ~4Kbit EPROM, ~64bit EEPROM
. Digital IP/Lib : 1.8V/5V Std. Cell Lib, IO Lib, and 1.8V Memory Compiler
. SPICE model including Mismatch & Noise, Cadence PDK
0.11um Digital + Analog
- 0.13um channel length with 0.11um shrunk BEOL
- Support Various Vop (1.0, 1.2, 1.5, 2.5, 3.3, 5V)
- ULP (Ultra Low LKG + Low Noise + Low Op.)
- Available RF process with 4um Al Inductor
- TS11 Process Overview
. Optical Shrink Process (90%) of 0.13um Foundry General Process
. eNVM : ~32bit Poly fuse, ~512Kbit EPROM (eMemory), ~128KbitAnti fuse (Kilopass)
. Digital IP/Lib : Multi Vth Std. Cell Lib, IO Lib, Memory Compiler
. SPICE model including Mismatch & Noise, Cadence PDK
- ULP11 Process Overview
. Focus on Low Power + Ultra Low Leakage + Low Power Operation, Able to Minimize both Active Power Consumption
and Leakage in off-status in one technology
. PNO gate oxide is used for lower 1/f noise
. 1.5V Low Power & 1.2V Ultra Low LKG.
